Freescale MC9S08MP16电机控制方案

日期:2009-12-01 20:55:58   浏览次数:5564   

Freescale 公司的MC9S08MP16是低成本8位MCU,用于工业和汽车中夹种速度的马达控制,能提供安全的,精确和低成本的马达控制. MC9S08MP16采用8位HCS08 CPU,2.7V-5.5V和–40℃到125℃温度范围内,CPU速度高达40 MHz,支持48个中断/重置源, 16KB 闪存, 1KB RAM,马达控制专用的1x 2-ch + 1x 6ch FlexTimer,3x高速模拟比较器,可编程增益放大器,2x可编程延迟区块,13路12位2.5us转换时间的ADC.本文介绍了MC9S08MP16主要特性, 方框图和DEMO9S08MP16 评估板详细电路图.

The S08MP16 is a low cost 8-bit MCU that delivers Safe, Accurate and Inexpensive Motor Control for a wide speed range of Industrial and Automotive applications. An ideal entry-level solution for Brushless DC (BLDC) motor applications it features an 8 channel PWM/Flextimer module providing hardware dead-time insertion, Analogue Comparators, Programmable Gain Amplifier, and a 12-bit ADC with PWM hardware triggering. Also offered is an Independently Clocked COP & Cyclic Redundancy Check (CRC) Engine providing clock failure protection & memory content validation for safety-critical applications implementing IEC60730.


• 8-Bit HCS08 Central Processor Unit (CPU)

– Up to 51.34 MHz CPU at 2.7V to 5.5V across temperature range of –40°C to 105℃

– Up to 40 MHz CPU at 2.7V to 5.5V across temperature range of –40°C to 125℃

– HC08 instruction set with added BGND instruction and additional addressing modes for LDHX and STHX Support for up to 48 interrupt/reset sources

• On-Chip Memory

– Up to 16 KB flash memory; read/program/erase over full operating voltage and temperature

– Up to 1 KB random-access memory (RAM)

– Security circuitry to prevent unauthorized access to RAM and flash memory contents

• Power-Saving Modes

– Two low power stop modes; reduced power wait mode

– Peripheral clock gating can disable clocks to unused modules

• Clock Source Options

– Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25–38.4 kHz or 1–16 MHz

– Internal Clock Source (ICS) — Containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolutions and 2% deviation over temperature and voltage; supports CPU frequencies up to 51.34 MHz

• System Protection

– Watchdog computer operating properly (COP) reset running from dedicated 1-kHz internal clock source or bus clock

– Low-voltage detection with reset or interrupt; selectable trip points

– Illegal opcode and illegal address detection with reset

– Flash memory block protection

• Development Support

– Single-wire background debug interface

– Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus three more breakpoints in on-chip debug module)

– On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints

• Peripherals

– IPC — Interrupt Priority Controller with 4 programmable interrupt priority levels

– ADC—13-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/℃ temperature sensor; internal bandgap reference channel; operation in stop3

– PGA — Differential programmable gain amplifier with programmable gain (x1, x2, x4, x8, x16, or x32)

– HSCMP — Three fast analog comparators with positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering; windowing; HSCMP1 and HSCMP2 outputs can be optionally routed to FTM1 module; runs in stop3

– DAC — Three 5-bit digital to analog convertor used as a 32-tap voltage reference for each comparator

– PDB — Two programmable delay blocks: PDB1 synchronizes PWM with samples of ADC; PDB2 synchronizes PWM with comparing window of analog comparators

– SCI — Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge

– SPI — Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting

– IIC/SMBus — Up to 400 kbps; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing; SMBus compatible

– FTM — Two Flextimers with total of 8 channels; One 2-channel (FTM1) and one 6-channel (FTM2);supports operation up to 2x bus clock; selectable input capture, output compare, edge- or center-aligned PWM; dead time insertion; fault inputs

– MTIM — 8-bit modulo counter with 8-bit prescaler

– RTC — (Real-time counter) 8-bit modulus counter with binary or decimal based prescaler; External clock source for precise time base, time-of-day, calendar or task scheduling; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components, runs in all MCU modes

– CRC — Cyclic redundancy check generator

– KBI — Three 8 channel keyboard interrupt module with software selectable polarity on edge or edge/level modes

• Input/Output

– 40 GPIOs, 2 output-only pins.

– Hysteresis and configurable pull up device on input pins; Configurable slew rate and drive strength on output pins; Sink/Source current up to 20mA

• Package Options

– 48-LQFP, 32-LQFP, 28-SOIC 48-LQFP qualified for automotive usage


Industrial drives/fans/pumps  

HVAC systems

Actuator systems

Medical equipment (infusion pumps, respirators, analyzers)

Office Equipment

Small appliance/personal care (food processors, shavers)

Automotive electrical fuel pump

Automotive window lift

Automotive fan control

Automotive high-brightness LEDs


图2.DEMO9S08MP16 评估板外形图

The DEMO9S08MP16 is a cost-effective demo platform for evaluating and developing with the Freescale MC9S08MP16. This low-cost 8-bit MCU is designed to deliver smooth, efficient and safe sensorless BLDC motor control across a wide speed range of industrial and automotive applications.

Peripherals include but are not limited to two 16-bit FlexTimers with deadtime insertion and fault protection in hardware, three high-speed analog comparators, a 6-ch., 16-bit PWM module with emergency over-current shutdown protection, a programmable gain amplifier and a 12-ch., 12-bit ADC with PWM hardware triggering. Also included are an independently clocked COP and cyclic redundancy check (CRC) engine delivering CLK failure protection and memory content validation for safety-critical applications.

图3.DEMO9S08MP16 评估板电路图(1)

图4.DEMO9S08MP16 评估板电路图(2)

图5.DEMO9S08MP16 评估板电路图(3)

图6.DEMO9S08MP16 评估板电路图(4)

图7.DEMO9S08MP16 评估板电路图(5)

图8.DEMO9S08MP16 评估板电路图(6)

图9.DEMO9S08MP16 评估板电路图(7)

图10.DEMO9S08MP16 评估板电路图(8)

图11.DEMO9S08MP16 评估板电路图(9)

图12.DEMO9S08MP16 评估板电路图(10)