CY37064解密

日期:2012-05-18 08:16:33   浏览次数:2973   

CY37064解密

致芯科技专门针对CYPRESS的CPLD进行研究,成功对CY37064解密CY37128解密。CYPRESS的CPLD解密主要包括CY37032解密CY37064解密CY37128解密C737192解密CY37256解密CY37384解密CY37512解密。

 CY37064是一款可以重复擦写的CMOS工艺的复杂逻辑电路CPLD。具有JTAG调试仿真接口,不同的设计无需对输入输出管脚改变也无误对时序做任何改变。CY37064是输入CYPRESS公司的ULTRA37000系列中的产品,所有的ULTRA37000系列CPLD都是可以在线编程擦写的复杂CPLD电路,具有3.3V和5V两种工作电压,封装形式上有PLCC PQFP QFP BGA等封装,解密后可以提供JEDEC格式的JED文件,CY37064解密首选致芯科技,深圳CY37064解密浙江CY37064解密都可以当天提供程序。

CY37064 Features:
  In-System Reprogrammable? (ISR?) CMOS CPLDs
  —JTAG interface for reconfigurability
  —Design changes do not cause pinout changes
  —Design changes do not cause timing changes
  High density
  —32 to 512 macrocells
  —32 to 264 I/O pins
  —Five dedicated inputs including four clock pins
  Simple timing model
  —No fanout delays
  —No expander delays
  —No dedicated vs. I/O pin delays
  —No additional delay through PIM
  —No penalty for using full 16 product terms
  —No delay for steering or sharing product terms
  3.3V and 5V versions
  PCI-compatible[1]
  Programmable bus-hold capabilities on all I/Os
  Intelligent product term allocator provides:
  —0 to 16 product terms to any macrocell
  —Product term steering on an individual basis
  —Product term sharing among local macrocells
  Flexible clocking
  —Four synchronous clocks per device
  —Product term clocking
  —Clock polarity control per logic block
  Consistent package/pinout offering across all densities
  —Simplifies design migration
  —Same pinout for 3.3V and 5.0V devices
  Packages
  —44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,BGA, and Fine-Pitch BGA packages